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| R8A20211BG/R8A20210BG (MARIE_Blade) Network Address Search Engine (9 M/18 M-bit Full Ternary CAM) REJ03H0001-0100 Rev.1.00 Feb 21, 2005 Description Renesas delivers MARIE_Blade that is a ternary CAM search engine targeted for network packet classifying. The fullcustom CAM memory realizes large capacity, high density and low power consumption. www..com MARIE_Blade can realize up to 133 Msps in 72-bit/144-bit normal mode (parallel search 266 Msps), 66.5 Msps in 288bit mode (parallel search 133 Msps) and 33 Msps in 576-bit mode (parallel search 66.5 Msps). The Hierarchical search reduces power consumption; The DX test logic, an extended bit, performs a DX test logic search first (primary search), and the DQ pin performs a DQ array search (secondary search). The parity bit in the DQ array can check for errors as an additional function. Features * * * * * * * * * * * * * * * 9 M/18 M-bit full ternary CAM CLK operating frequency 266 MHz Max Maximum search rate at normal mode: 133 Msps [72-bit/144-bit lookup size] Maximum search rate at parallel mode: 266 Msps [72-bit/144-bit lookup size] Maximum search rate at normal mode: 66.5 Msps [288-bit lookup size] Maximum search rate at parallel mode: 133 Msps [288-bit lookup size] Maximum search rate at parallel mode: 33 Msps [576-bit lookup size] Maximum search rate at normal mode: 66.5 Msps [576-bit lookup size] Priority encoder Hierarchical search Parity bit (even parity) check IEEE 1149.1 test port 1.2 V core power supply 1.2 V power supply for search (1.0 V power supply for power saving) SSTL-2 interface/2.5 V I/O power supply Rev.1.00 Feb 21, 2005 page 1 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Block Diagram DX DQ CLK P_THROUGH F_SEL Search Key PLL JTAG Search Data TDI TDO TMS TCK TRST PHSL RSTL DQ Search Key Control Register Search Mask Register Test_I Test_O Test WDQS DX Test Logic www..com Chip Select OP.Enable OP.Code MDS DX Full Ternary CAM DQ Array Priority Encoder RDQS Parity Bit Local Winner Index Address Global Winner DQ DQ[71:0] Write Mask Register Read Data_VALID Index_VALID DX[3:0] Write Data DX Write Data DQ Error Check Rev.1.00 Feb 21, 2005 page 2 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Functional Description 1. High Density and Low Power Consumption Renesas MARIE_Blade is a network search engine with the high-density TCAM memory cell. The minimized memory cell allows MARIE_Blade to realize not only high performance but also small dimension and low power consumption. 2. SSTL-2 Interface SSTL2 class-1/2 can be selected depending on system board specifications. Exception: the external Vref pin provides the input reference voltage. 3. Programmable Array Type of array architecture does not determine a lookup size, but the basic unit of entry address for Write TCAM is 72-bit wide. Each lookup size, 72-bit/144-bit/288-bit/576-bit, for secondary search is specified when a command is loaded: Lookup result provided by the Index Address also depends on the lookup size used. www..com Chip Image DX Test Logic DQ Array 72-bit x 16K entry (/Block) 144-bit x 8K entry (/Block) 288-bit x 4K entry (/Block) 576-bit x 2K entry (/Block) Total: 16 Blocks Figure 1 Block Structure 4. Bank Structure The MARIE_Blade CAM array is comprised of two banks, which enables to perform a search in parallel. The number of block in each bank is programmable and determined by the bankset register setting. The whole 16 blocks are divided to any sizes. Refer to the example on the figure 2. Chip Image Block14 Block12 Block10 Block8 Block15 Block13 Block11 Block9 Block0 Block2 Block4 Block6 Block15 Block13 Block11 Block9 Block1 Block3 Block5 Block7 Block14 Block12 Block10 Block8 DQ Array 16 Blocks can be divided into two banks according to the serial number shown on the block. Block1 Block3 Block5 Block7 Block0 Block2 Block4 Block6 : Bank0 : Bank1 Figure 2 Bank Structure Example Rev.1.00 Feb 21, 2005 page 3 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) 5. Greedy Operation MARIE_Blade offers the Greedy operation to write to the DQ array. In the Greedy operation, Block 0-7 (figure 2) are defined as Mat A, and Block 8-15 are defined as Mat B. The Greedy writes to an entry in each Mat at a time (total two entries). The DQ pin [17:0] carries an address for access, but its value [17] selecting either MAT A or MAT B is ignored in this case. 6. Hierarchical Search MARIE_Blade has two types of search: the DX test logic search and the DQ array search. The DX Test Logic consists of 4-bit entry, and DQ array, 72-bit entry. MARIE_Blade searches the DX Test Logic (primary search) first, and then searches only the DQ array having a hit address of primary search (secondary search). Therefore the Hierarchical Search can reduce power consumption. Each block in the DX Test Logic has a single kind of data. Note: MARIE_Blade is not partitioned by configuration (72-bit/144-bit/288-bit/576-bit). If the user does not utilize the DX Test Logic search, MARIE_Blade searches the entire DQ array. www..com DQ Secondary Search DX Test Logic DX HIT! DX Test Logic MISS Block Primary Search DQ Array DQ Array Block DX Test Logic MISS DX Test Logic MISS DQ Array Block The Secondary Search operates only in the block with the Primary Search hit. DQ Array Block Figure 3 Hierarchical Search 7. Global Mask Search Register The Global Mask Search Register (GMSR) controls bits that participate in the secondary search. The GMSR mask consists of the same bit width as that of corresponding CAM DQ, and it masks per bit. The GMSR is valid only during the secondary search. Note that the operation of other registers is restricted during the parallel mode. Please refer to another section for details. Search Comparison Data DQ Global Mask 0 1 1 X 1 1 X 0 TCAM DQ Array The GMSR bit width is the same as that of DQ. 1-bit GMSR masks 1-bit DQ search key. Figure 4 Global Mask Search Rev.1.00 Feb 21, 2005 page 4 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) 8. Write Mask Register The Write Mask Register (WMR) controls bits that participate in the Write TCAM operation. The WMR mask has the same bit width as that of corresponding CAM DQ array. Also, this register is valid only during Write TCAM. When writing to the 9 M Mats simultaneously (Greedy Operation), MARIE_Blade uses the mask register that is shared between MAT A and Mat B (Greedy Write). 1 01101 Write Mask DQ DQ Write Data Former value www..com DQ DQ Former value DQ TCAM DQ Array The WMR bit width is the same as that of DQ. 1-bit WMR masks 1-bit DQ. Figure 5 Masked Write TCAM 9. Address Source and Data Source A couple of different sources can be selected to write addresses and/or data into the DQ array. Two possible sources for the address input are the DQ input pin and the Address Source Register (ASR). Three possible sources for data input are the DQ input pin, the Data Source Register (DSR), or the Load Data Register (LDR). Address Source Register (ASR) There are two sources to input entry addresses to the DQ array: The DQ pin and ASR. An entry address with a hit is stored in the ASR so that the DQ pin can trace hit history with this ASR. In addition, ASR is capable of detecting empty entries as Pseudo Learn. Data Source Register (DSR) The DQ input pin, DSR or LDR can be used as a data source. DSR stores data of search miss. Pseudo Learn and Write TCAM to the array can be realized by specifying the DSR having search miss data (data source). Rev.1.00 Feb 21, 2005 page 5 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Load Data Register (LDR) Load Data Register (LDR) is used as the write data source in order to operate Move. See the figure 6. The Load Data command loads the DQ data into the LDR first, and then operates the Write TCAM with this LDR (source register). Please refer to another section for details. 1. Load Data Entry to be transferred 2. Reset All Bits to "0" LDR 3. Write TCAM Destination TCAM Array www..com Move Sequence Load data to the LDR Reset the original data to "0" Data from LDR to Write TCAM Figure 6 Move 10. Pseudo Learn MARIE_Blade does not support an ordinary Learn function required by LAN switch for example. However, with a combination of DSR and ASR, Pseudo Lean can take the place of Learn. A search key resulting in a miss is stored into the DSR. Then Pseudo Learn can be achieved by operating Write TCAM with the DSR. Furthermore, search for empty entries can be added into this process. In this case, the data to be input must contain an entry flag bit. There is an example of 72-bit Normal Search. The user must select MSB [71] DQ data as the empty entry flag bit, and set it to be [even, odd] = [0, 1] respectively (1 bit consists of even and odd). If there is any empty entry indicating [1, 0], it means all data are occupied. In other words, all data in the TCAM must be [0, 1] after reset, and bit-1 [71] must be always [even, odd]= [1,0] during the Write TCAM. After setting a rule likewise, the procedure follows... (1) When a search miss occurs, store the search miss key into the DSR (2) Stop searching when the DSR is full of search miss keys (3) Search only the DQ MSB with GMSR (Search key, DQ [71] = 0, detects empty entries) (4) Store the hit address of (3) (5) Do the Write TCAM with (1) DSR data and (4) ASR address The Write Delete Entry command can facilitate to reset empty entry bits. This command resets all bits in the assigned entry to be [even, odd] = [0,1]. Search key DQ DX Search Miss DSR Pseudo Learn TCAM Array What is Pseudo Learn? Normal Search Search Miss Store Search Miss Key into DSR Write TCAM with data in DSR If it is not clear where an empty entry is, search sequence for empty entry is needed. Figure 7 Pseudo Learn Rev.1.00 Feb 21, 2005 page 6 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) 11. Parity Bit Check MARIE_Blade provides an error check function using parity bits. Soft error can be detected with upper 2 bits in each DQ entry (72-bit lookup) as the parity bit. If Status Set Register (ST) is set to allow the error check, Parity Bit Check is automatically operated during Read TCAM. Once any error is found, the error flag goes high and retrieved data is input. Go through the following steps to provide the parity bit for 72-bit entry. >> DQ [70] ... Set even bits in DQ [69:0] to be even parity >> DQ [71] ... Set odd bits in DQ [69:0] to be even parity Note that MARIE_Blade supports neither Error Check & Correct nor Parity Bit Generation. www..com Rev.1.00 Feb 21, 2005 page 7 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Pin Description * Common: 13 pins Pin Name Clock input Symbol CLK I/O I Function CAM Clock. All input signals except OP and DQ reference to rising edge of CLK. Activates all output signals except IND, LW and GW in order to control. Asserted in half operating frequency range. This signal and CLK generate internal CAM_CLK providing Cycle-A and Cycle-B. Please refer to another section for details. Bypasses the PLL circuit. Refer to the Block Diagram. Setting "L" operates PLL. Specifies PLL Lock Range depending on CLK operation frequency. Refer to the Table 1. Source Synchronous Clock for input signals from OP and DQ. Source Synchronous Clock for output signals from IND, LW and GW. Hardware reset for MARIE-Blade. Phase L PHSL I PLL through Frequency select www..com P_THROUGH F_SEL WDQS RDQS RSTL I I I O-Tri I WDQS [4:0] RDQS Reset L * Network Processor/ASIC Interface: 110 pins Pin Name Chip select Operation enable Mode select Op.code [6:0] DX [3:0] DQ/address [71:0] Index address [17:0] Symbol C_SEL OP_ENA MDS OP[6:0] DX[3:0] DQ[71:0] IND[17:0] I/O I I I I I/O-Tri I/O-Tri O-Tri Function Enables only chips with High. This signal must be asserted during two cycles, Cycle-A and Cycle-B. Indicates that commands from OP are valid. This signal must be set during two cycles, Cycle-A and Cycle-B. Selects Normal or Parallel for search, and Normal or Greedy for write. OP [6:0] controls command codes. Should be asserted at Cycle-A Extended Data Primary search key is input/output when DX Test Logic Read/Write/Search command is loaded. Data Pin Multiplexed pin between address and data, which functions during DQ array Read/Write/Search command. Input address into externally located SRAMs. Entry address carried by this pin is search hit address. If ASR is used as write address source, IND retrieves write address from it. Goes high when search results in hit. Directly outputs prioritized device ID set by ST [9:8] when search results in hit. Qualifies read data when DQ/DX output. Qualifies read data when IND outputs regardless of search result. Goes high when Party Bit Check finds any errors. Enable only during a Read TCAM, whose setting allows error check. Local winner flag Global winner flag [1:0] Read data valid Index valid Error check flag LW GW RD_VD IND_VD EC_F O O-Tri O O O Rev.1.00 Feb 21, 2005 page 8 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) * JTAG Interface: 5 pins Pin Name Test mode select Test data input Test data output Test clock Symbol TMS TDI TDO TCK I/O I I O I Function Gives input command for TAP controller. Serial input of registers placed between TDI and TDO. Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP controller. Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are driven from the falling edge of TCK. JTAG reset TRST I JTAG reset can be used to reset TAP controller. Note: JTAG specification is referenced to IEEE 1149.1. * Power www..com and Ground Symbol V_CORE V_MAT VCCQ V_REF GND VPLL GPLL Pins 50 41 24 8 104 1 1 Function 1.2 V for core and peripheral circuitry Power to match line1.2 V to 1.0 V Supply voltage for I/O buffer = 2.5 V 50% of VCCQ 0 V Ground level 2.5 V 0 V Ground level for PLL Pin Name Vectored Voltage for search I/O buffer supply voltage Input reference voltage Ground Supply voltage for PLL Ground for PLL Follow the table below to input F_SEL depending on the CLK operation frequency range Table 1 F_SEL Input Value for CLK Operation Frequency Range F_SEL [2] 0 0 0 0 F_SEL [1] 1 1 0 0 F_SEL [0] 1 0 1 0 Input CLK (MHz) 250 to 350 150 to 225 125 to 175 75 to 112.5 Rev.1.00 Feb 21, 2005 page 9 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Pin Layout 1. Signal Ball Name A2 A23 A24 B1 B2 B3 B4 B22 B23 www..com B24 B25 C1 C3 C4 C22 C23 C25 D1 D2 D3 D23 D24 D25 E2 E4 E22 E24 F1 F2 F4 F22 F24 F25 Pin Name DQ [71] DQ [34] DQ [35] DQ [70] DQ [69] DQ [68] DQ [67] DQ [30] DQ [31] DQ [32] DQ [33] DQ [66] DQ [65] DQ [64] DQ [27] DQ [28] DQ [29] DQ [63] DQ [62] WDQS [3] WDQS [1] DQ [25] DQ [26] DQ [61] DQ [60] DQ [23] DQ [24] DQ [59] DQ [58] DQ [57] DQ [20] DQ [21] DQ [22] Ball Name G1 G3 G4 G22 G23 G25 H1 H2 H3 H23 H24 H25 J2 J3 J23 J24 K1 K2 K4 K22 K23 K24 K25 L1 L23 L25 M1 M2 M3 M4 M22 M24 M25 Pin Name DQ [56] DQ [55] DQ [54] IND [17] DQ [18] DQ [19] RD_VD P_THROUGH F_SEL [2] IND [14] IND [15] IND [16] F_SEL [1] F_SEL [0] IND [12] IND [13] DX [3] DX [2] DX [1] RDQS IND [9] IND [10] IND [11] DX [0] PHSL GW [1] MDS C_SEL WDQS [4] RSTL CLK TEST_O GW [0] Ball Name N2 N24 P1 P2 P3 P4 P24 P25 R1 R3 R24 R25 T1 T2 T23 T24 T25 U2 U3 U23 U24 V1 V2 V3 V22 V23 V24 V25 W1 W3 W22 W23 W25 Pin Name OP_ENA TEST_I [0] OP [0] OP [1] OP [2] OP [3] TEST_I [1] LW OP [4] OP [5] TEST_I [2] IND_VD OP [6] TMS EC_F IND [1] IND [0] TCK TRST IND [3] IND [2] TDI TDO DQ [36] IND [7] IND [6] IND [5] IND [4] DQ [37] DQ [38] DQ [1] DQ [0] IND [8] Ball Name Y1 Y2 Y4 Y22 Y24 Y25 AA2 AA4 AA22 AA24 AB1 AB2 AB3 AB23 AB24 AB25 AC1 AC3 AC4 AC22 AC23 AC25 AD1 AD2 AD3 AD4 AD22 AD23 AD24 AD25 AE2 AE23 AE24 Pin Name DQ [39] DQ [40] DQ [41] DQ [4] DQ [3] DQ [2] DQ [42] DQ [43] DQ [6] DQ [5] DQ [44] DQ [45] WDQS [2] WDQS [0] DQ [8] DQ [7] DQ [46] DQ [47] DQ [48] DQ [11] DQ [10] DQ [9] DQ [49] DQ [50] DQ [51] DQ [52] DQ [15] DQ [14] DQ [13] DQ [12] DQ [53] DQ [17] DQ [16] Rev.1.00 Feb 21, 2005 page 10 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) 2. Power/Ground * VCCQ Ball Name A1 A25 C2 C24 E1 E25 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ball Name G2 G24 J1 J25 L2 N1 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ball Name N25 R2 U1 U25 W2 W24 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ball Name AA1 AA25 AC2 AC24 AE1 AE25 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ * V_CORE www..com Ball Name A3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE Ball Name A17 A18 A19 A20 A21 D4 D22 E3 E23 F3 F23 K3 T3 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE Ball Name Y3 Y23 AA3 AA23 AB4 AB22 AE3 AE5 AE6 AE7 AE8 AE9 AE10 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE Ball Name AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE * V_MAT Ball Name D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT Ball Name D16 D17 D18 D19 D20 D21 H4 H22 J4 J22 U4 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT Ball Name U22 V4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT Ball Name AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT * VREF Ball Name A4 A22 Pin Name VREF VREF Ball Name L4 N22 Pin Name VREF VREF Ball Name R4 R23 Pin Name VREF VREF Ball Name AE4 AE22 Pin Name VREF VREF Rev.1.00 Feb 21, 2005 page 11 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) * GND Ball Name B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 www..com B16 B17 B18 B19 B20 B21 C5 C6 C7 C8 C9 C10 C11 C12 C13 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball Name C14 C15 C16 C17 C18 C19 C20 C21 L3 L11 L12 L13 L14 L15 L22 L24 M11 M12 M13 M14 M15 M23 N3 N4 N11 N12 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball Name N13 N14 N15 N23 P11 P12 P13 P14 P15 P23 R11 R12 R13 R14 R15 T4 T22 W4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball Name AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND * VPLL/GPLL Ball Name P22 Pin Name VPLL Ball Name R22 Pin Name GPLL Rev.1.00 Feb 21, 2005 page 12 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ A VCCQ DQ[71] VREF VREF DQ[34] DQ[35] VCCQ A CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE B DQ[70] DQ[69] DQ[68] DQ[67] GND C DQ[66] VCCQ DQ[65] DQ[64] GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DQ[30] DQ[31] DQ[32] DQ[33] B GND DQ[27] DQ[28] VCCQ DQ[29] C WDQS V_ V_ WDQS D DQ[63] DQ[62] V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT DQ[25] DQ[26] D [3] CORE CORE [1] E VCCQ DQ[61] F DQ[59] DQ[58] V_ DQ[60] CORE V_ DQ[57] CORE DQ[23] DQ[20] V_ DQ[24] VCCQ E CORE V_ DQ[21] DQ[22] F CORE www..com G DQ[56] VCCQ DQ[55] DQ[54] P_TH F_SEL H RD_VD ROU V_MAT [2] GH J VCCQ F_SEL F_SEL V_MAT 1 [0] V_ DX[1] CORE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DQ[17] DQ[18] VCCQ DQ[19] G V_MAT IND[14] IND[15] IND[16] H V_MAT IND[12] IND[13] VCCQ J RDQS IND[9] IND[10] IND[11] K GND PHSL GND GW[1] L CLK GND TEST GW[0] M _O TEST VCCQ N _I[0] TEST _I[1] LW P K DX[3] DX[2] L DX[0] VCCQ GND VREF M MDS C_SEL N VCCQ OP_ ENA WDQS RSTL [4] GND GND VREF GND VPLL GND P OP[0] OP[1] OP[2] OP[3] R OP[4] VCCQ OP[5] VREF T OP[6] TMS U VCCQ TCK V TDI V_ GND CORE TRST V_MAT TEST IND_ R GPLL VREF _I[2] VD GND EC_F IND[1] IND[0] T V_MAT IND[3] IND[2] VCCQ U IND[7] IND[6] IND[5] IND[4] V DQ[1] DQ[0] VCCQ IND[8] W DQ[4] DQ[6] V_ DQ[3] DQ[2] Y CORE V_ DQ[5] VCCQ AA CORE TDO DQ[36] V_MAT W DQ[37] VCCQ DQ[38] GND Y DQ[39] DQ[40] AA VCCQ DQ[42] AB DQ[44] DQ[45] V_ DQ[41] CORE V_ DQ[43] CORE WDQS V_ V_ WDQS V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT DQ[8] DQ[7] AB [2] CORE CORE [0] GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DQ[11] DQ[10] VCCQ DQ[9] AC GND DQ[15] DQ[14] DQ[13] DQ[12] AD AC DQ[46] VCCQ DQ[47] DQ[48] GND AD DQ[49] DQ[50] DQ[51] DQ[52] GND AE VCCQ DQ[53] 1 2 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ VREF DQ[17] DQ[16] VCCQ AE VREF CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (Top view) Rev.1.00 Feb 21, 2005 page 13 of 14 R8A20211BG/R8A20210BG (MARIE_Blade) Package Dimensions 361F7X-A 27 0.2 24 0.2 A 2.6MAX 361pin 27 x 27mm body BGA B 0.6 0.1 0.25 M C AB www..com aaa 0.5 0.1 1pin corner C Package Coplanarity Dimension Minimum Normal Maximum aaa -- -- 0.15 AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12131415161718192021222324 25 1.0 x 24 = 24 1 27 0.2 24 0.2 1 1.0 x 24 = 24 Rev.1.00 Feb 21, 2005 page 14 of 14 |
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